Semiconductor integrated circuit device, and method of manufacturing the same

专利摘要:
In a DRAM having a capacitor over bit line structure in which the capacitor insulating film of the information storage capacitor C is made of a high dielectric material such as a Ta 2 O 5 (tantalum oxide) film 46, the information storage capacitor C ), The capacitor insulating film is formed by forming at least a portion of the bit line BL disposed below the layer and the wirings 23 to 26 in the first layer of the peripheral circuit that are in contact with the silicon oxide film 28 in the base portion. Due to the high temperature heat treatment performed at the time of formation, the adhesion of the interface between the bit line BL, the wirings 23 to 26 and the silicon oxide film 28 is improved.
公开号:KR19990068074A
申请号:KR1019990001957
申请日:1999-01-22
公开日:1999-08-25
发明作者:사이토마사요시；나카무라요시타카；카와키타케이죠；야마다사토루；세키구치토시히로；아사노이사무；후쿠다타쿠야；타마루쯔요시；후쿠다나오키；아오키히데오；히라사와마사요시；고토히데카즈；타다키요시타카；스즈키마사유키
申请人:가나이 쓰토무；가부시키가이샤 히타치세이사쿠쇼；
IPC主号:

专利说明:

Semiconductor integrated circuit device and manufacturing method therefor {SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD OF MANUFACTURING THE SAME}
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly, to a technology effective in application to a semiconductor integrated circuit device having a dynamic random access memory (DRAM).
A memory cell of a DRAM is disposed at an intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form on a main surface of a semiconductor substrate, and includes one memory cell selection MISFET and one information storage capacitor connected in series thereto. Capacitor). The memory cell selection MISFET mainly consists of a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions constituting a source and a drain. The bit line is disposed above the memory cell selection MISFET and electrically connected to one of a source and a drain. The information storage capacitor is similarly disposed above the memory cell selection MISFET and electrically connected to the other of the source and the drain.
As described above, in order to compensate for the reduction in the accumulated charge amount of the information storage capacitor due to the miniaturization of the memory cell, the DRAM has a so-called stacked capacitor structure in which the information storage capacitor is disposed above the memory cell selection MISFET. I adopt it. In the DRAM employing the stacked capacitor structure, a capacitor under bitline (CUB) structure in which an information storage capacitor is disposed below the bit line, and an information storage capacitor in an upper portion of the bit line are disposed. There is a Capacitor Over Bitline (COB) structure.
Of the two types of stacked capacitor structures described above, the COB structure in which the information storage capacitor element is disposed above the bit line is more suitable for the miniaturization of the memory cell than the CUB structure. It is necessary to increase the surface area by increasing the accumulated charge amount of the miniaturized information storage capacitor, but in the case of the CUB structure in which the bit line is disposed on the upper portion of the information storage capacitor, the bit line and the memory are increased. This is because the aspect ratio of the contact hole connecting the cell selection MISFET becomes extremely large, which makes it difficult to open the hole.
In addition, the recent large capacity DRAM of 64 Mbit (megabit) or 256 Mbit makes it difficult to secure the amount of accumulated charge only by increasing the surface area by three-dimensional information storage capacitive elements, and parallel with the three-dimensional capacity of the capacitive elements. The capacitive insulating film is composed of a high dielectric material such as Ta ₂ O ₅ (tantalum oxide), (Ba, Sr) TiO ₃ (barium strontium titanate; hereinafter referred to as BST), and SrTiO ₃ (strontium titanate; STO). It is considered. A DRAM having a capacitive insulating film made of such a high dielectric material is described in, for example, Japanese Patent Laid-Open No. Hei 1-222469 and USP 5,383,088.
In the 64-256 Mbit DRAM described above, as a countermeasure against signal delay due to an increase in chip size, a metal material having a lower resistance than that of a polycrystalline silicon film is employed as a material for a word line or a bit line, or a source, a drain, and a MISFET. As a countermeasure against the increase in resistance caused by the miniaturization of the contact hole connecting the wiring, TiSi ₂ (titanium silicide) or CoSi is formed on the surface of the source and drain of the MISFET constituting a peripheral circuit such as a sense amplifier or a word driver requiring high speed operation. _It is considered to be inevitable to employ a silicidation technique for forming a high melting point metal silicide layer such as ₂ (cobalt silicide). This silicidation technique is described in, for example, Japanese Patent Laid-Open Nos. 6-29240 and 8-181212.
In DRAMs corresponding to 256 Mbit and later generations, the gate electrode (word line) of the MISFET for memory cell selection and the gate electrode of the MISFET of the peripheral circuit, such as W (tungsten), as a signal delay countermeasure against the increase in chip size. A high melting point metal silicide layer is formed on the surface of the source and drain of the MISFET constituting the peripheral circuit as a countermeasure to reduce the contact resistance of the diffusion layer and the wiring as well as the low resistance material mainly composed of the high melting point metal. Form.
In addition, as a countermeasure against the delay of the bit line, the DRAM is composed of a low resistance material mainly composed of a high melting point metal such as W, and at the same time, the first layer of the bit line and the peripheral circuit as a countermeasure for reducing the wiring forming process. Are simultaneously formed in the same process. In addition, the DRAM adopts a COB structure in which an information storage capacitor is disposed above the bit line as a countermeasure to secure the amount of charge accumulated in the information storage capacitor. ₂ O ₅ is composed of a high-dielectric material such as (tantalum oxide).
By the way, the present invention has examined the DRAM manufacturing process as described above, and the bit line formed on the MISFET and the wiring of the first layer of the peripheral circuit are performed in the step of forming the next information storage capacitor. The phenomenon which peeled from the insulating film surface by the high temperature heat processing was discovered.
Here, the outline of the process for manufacturing such DRAM will be briefly described. First, a low-resistance material mainly composed of a high melting point metal deposited on a main surface of a semiconductor substrate is patterned to form a gate electrode (word line) of a MISFET for selecting a memory cell. ) And the gate electrode of the MISFET of the peripheral circuit, and then ion implantation of impurities into the semiconductor substrate to form the source and drain of these MISFETs.
Next, after covering the upper part of these MISFETs with an insulating film, a contact hole is formed first in the insulating film in the upper part of the source and drain of a memory cell selection MISFET, and a plug of polycrystalline silicon is then embedded in this contact hole. Next, after forming contact holes in the insulating films on the gate electrodes, the sources, and the drains of the MISFETs in the peripheral circuits, a high melting point metal such as a Ti film or a Co film is formed on the insulating films including the inside of these contact holes. A thin film is deposited, and then the semiconductor substrate is heat treated to react the substrate Si at the bottom of the contact hole with the high melting metal film to form a high melting point metal silicide layer at the bottom of the contact hole.
Next, a wiring material mainly containing a high melting point metal film such as W is deposited on the upper portion of the insulating film including the inside of the contact hole of the peripheral circuit, and then patterning the wiring material and the unreacted Ti film remaining on the surface of the insulating film. The bit line and the wiring of the first layer of the peripheral circuit are formed on the insulating film. The bit line is electrically connected to one of a source and a drain of the memory cell selection MISFET through the contact hole in which a plug of polycrystalline silicon is embedded. The wiring of the first layer of the peripheral circuit is electrically connected to any one of a gate electrode, a source, and a drain of the MISFET of the peripheral circuit through the contact hole of the peripheral circuit.
Next, the upper part of each of the bit lines and the wirings of the first layer of the peripheral circuit is covered with an interlayer insulating film, and then one of the source and drain of the memory cell selection MISFET and the information storage capacitor are connected to the interlayer insulating film. After the through holes are formed, a conductive film such as polycrystalline silicon deposited on top of the through holes is patterned to form a lower electrode of the information storage capacitor having a three-dimensional structure.
Next, after depositing a high dielectric film such as Ta ₂ O ₅ (tantalum oxide) on the surface of the lower electrode, high temperature heat treatment is performed. A high-k dielectric film made of Ta ₂ O ₅ or a metal oxide such as BST or STO has a common property therein and needs to be subjected to high temperature heat treatment at about 800 ° C. in an oxygen atmosphere after forming the film in order to reduce the leakage current. In addition, once the high temperature heat treatment has been performed, it is necessary to prevent exposure to high temperature of about 450 ° C. or higher in order to prevent deterioration of the film quality.
Thereafter, a conductive film such as a TiN film is deposited on top of the high dielectric film, and then the conductive film and the high dielectric film under the layer are patterned to form an upper electrode and a capacitor insulating film of the information storage capacitor.
However, according to the present invention, the DRAM manufacturing process is examined, and when the high temperature heat treatment is performed to improve the film quality of the Ta ₂ O ₅ film, the wiring of the first layer of the bit line or the peripheral circuit peels off the surface of the insulating film. The phenomenon was found. This is because if the Ti film used to form the Ti silicide layer at the bottom of the contact hole remains on the insulating film made of silicon oxide, peeling occurs at the interface between the Ti film and the silicon oxide, which is why Ti forms oxides as compared to Si. It is because it is easy to do it.
As a countermeasure against the peeling of the Ti film and the silicon oxide film by the high temperature heat treatment, a method of removing the unreacted Ti film remaining on the surface of the insulating film with an acidic etching solution after forming the Ti silicide layer on the bottom of the contact hole by heat treating the Ti film is performed. Is considered. However, in the process of forming contact holes in the insulating film on the source and drain of the MISFET of the peripheral circuit, contact holes are also formed on the gate electrode of the MISFET at the same time, so that the unreacted Ti film is removed by the etching solution after the formation of the Ti silicide layer. The etching liquid also penetrates into the contact holes formed on the lower surface of the lower surface of the gate electrode, and the metal film constituting the gate electrode is etched. Therefore, the above countermeasures are effective when the gate electrode is composed of a polycrystalline silicon film or polyside film (lamination film of polycrystalline silicon and high melting point metal silicide) that is resistant to an acidic etching solution. It is not applicable when an electrode is comprised.
As another countermeasure to prevent the interfacial separation between the Ti film and the silicon oxide film, the Ti film is heat-treated to form (or at the time of forming) the Ti silicide layer, followed by heat treatment in a nitrogen atmosphere, whereby the Ti film has good adhesion to the silicon oxide film. A method of replacing with a (titanium nitride) film is contemplated. However, it is difficult to completely replace the Ti film on the silicon oxide film with the TiN film by the high temperature heat treatment in a nitrogen atmosphere, and even if the surface of the film is nitrided, it is not completely nitrided until the interface with the silicon oxide film. In addition, performing the high temperature heat treatment for a long time promotes diffusion of impurities injected into the source and the drain of the MISFET, which leads to a problem of formation of a shallow junction.
SUMMARY OF THE INVENTION An object of the present invention is a DRAM in which a capacitive insulating film of an information storage capacitor is made of a high dielectric material, wherein defects in which the lower layer wiring is peeled off the surface of the insulating film by high temperature heat treatment performed to improve the film quality of the high dielectric material. It is to provide a technique to prevent.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
1 is an overall plan view of a semiconductor chip including a DRAM according to one embodiment of the present invention.
2 is an equivalent circuit diagram of a DRAM according to one embodiment of the present invention.
3 is a sectional view showing the principal parts of a semiconductor substrate, each of which shows a part of a memory array and a peripheral circuit of a DRAM according to one embodiment of the present invention.
4 is a schematic plan view of a semiconductor substrate showing a portion of a memory array of a DRAM according to one embodiment of the present invention.
5 to 38 are cross-sectional views of principal parts of a semiconductor substrate, illustrating a method for manufacturing a DRAM according to one embodiment of the present invention.
<Description of Drawing>
1 semiconductor substrate, 2P type well
3n type semiconductor region, 4 n type well
Silicon oxide film, 6 element isolation groove
7-gate oxide film
8A to 8C gate electrode
9n-type semiconductor region (source, drain)
9an-type semiconductor region (source, drain)
10n + type semiconductor region (source, drain)
11p + type semiconductor region (source, drain)
12, 13 silicon nitride film, 13s sidewall spacer
14n-type semiconductor region, 15p-type semiconductor region
16SOG membrane
17, 18 silicon oxide film, 19, 20 contact hole
21 plugs, 22 through hole
23-26 wiring, 27 photoresist film
28 silicon oxide film, 30 to 34 contact holes
35 plugs, 36 Ti film
37TiSi2 film, 38 silicon oxide film
39SOG film, 40TiN film
41, 42 W film, 43 photoresist film
44 Silicon oxide film, 45 lower electrode (accumulative electrode)
45A polycrystalline silicon film, 46Ta2O5 film
47 upper electrode (plate electrode), 48 through hole
49 plug, 50, 51 silicon oxide film
52, 53 wiring,
54 through hole, 55 plug
56 interlayer insulation film, 57 to 59 wiring
60, 61 through hole
62 plug, 63 second interlayer insulating film
70 Polycrystalline Silicon Film, 71 Through Hole
72 Sidewall spacer, 73 recessed groove
74 SOG film, 75 photoresist film
BL bit line, C information storage capacitor
MARY memory array, MC memory cell
Qn n Channel MISFET, Qpp Channel MISFET
MISFET for selecting Qs memory cell,
SA sense amplifier, WD word driver
WL word line,
Among the inventions disclosed herein, an outline of representative ones will be briefly described as follows.
(1) In the semiconductor integrated circuit device of the present invention, at least a portion of the silicon oxide-based first insulating film formed on the main surface of the semiconductor substrate is formed with wires extending so as to be in contact with the first insulating film. A capacitor having a capacitor insulating film formed of a high-k dielectric film at least partially formed on the second insulating film formed thereon is formed, and the conductive film constituting the wiring is formed on the first insulating film in contact with the first insulating film. And a high melting point metal or an oxide of a high melting point metal.
(2) In the semiconductor integrated circuit device of the present invention, a memory cell selection MISFET having a gate electrode integrally formed with a word line is formed in a first region on a main surface of a semiconductor substrate, and an oxide covering the memory cell selection MISFET is formed. A bit line electrically connected to one of a source and a drain of the memory cell selection MISFET and extending in contact with the first insulating film is formed on an upper portion of the silicon-based first insulating film, and is formed on the bit line. A bit having a DRAM formed on top of an insulating film, the DRAM having an information storage capacitor device having a capacitor insulating film electrically connected to the other of the source and the drain of the memory cell selection MISFET; A conductive film constituting a line may be formed of a high melting point metal other than titanium in a portion of the first insulating film in contact with the first insulating film, or It made of a refractory metal nitride.
(3) In the semiconductor integrated circuit device of the present invention, the high dielectric film in (2) is a tantalum oxide film subjected to heat treatment for crystallization.
(4) In the semiconductor integrated circuit device of the present invention, at least part of the conductive film constituting the gate electrode of the memory cell selection MISFET in the above (2) is made of a metal film.
(5) In the semiconductor integrated circuit device of the present invention, in (2), the MISFET of the peripheral circuit of the DRAM is formed in the second region on the main surface of the semiconductor substrate, and the silicon oxide system of the peripheral circuit covering the MISFET of the peripheral circuit. A first layer wiring is formed on the first insulating film and is electrically connected to any one of a gate electrode, a source, or a drain of the MISFET of the peripheral circuit and extends to contact the first insulating film. In the conductive film constituting the wiring line, a portion of the conductive film in contact with the first insulating film on the first insulating film is formed of a nitride of a high melting point metal or a high melting point metal except titanium.
(6) The semiconductor integrated circuit device of the present invention is open in the first insulating film in (5), and electrically connects the wiring of the first layer and the source or drain of the MISFET of the peripheral circuit. A titanium silicide layer is formed at the bottom of the contact hole.
(7) In the semiconductor integrated circuit device of the present invention, in (5), the conductive film constituting each of the bit line and the first layer wiring is a tungsten film.
(8) In the semiconductor integrated circuit device of the present invention, in (5), the wiring of the first layer is formed inside the contact hole, and a laminated film of a titanium film and a barrier metal film, or a titanium film. And a plug formed of a laminated film of a barrier metal film and a tungsten film, and are electrically connected to a source or a drain of the MISFET of the peripheral circuit.
(9) In the semiconductor integrated circuit device of the present invention, in (5), the gate electrode of the MISFET of the peripheral circuit is composed of a metal film.
(10) The semiconductor integrated circuit device of the present invention is characterized in that the first insulating film is a spin-on-glass film or a silicon oxide film deposited by a CVD method in (5) above. Integrated circuit device.
(11) The semiconductor integrated circuit device of the present invention is the second layer electrically connected to the wiring of the first layer on the silicon oxide-based third insulating film formed on the information storage capacitor element in (5) above. Wirings are formed, and at least a portion of the conductive film forming the wirings of the second layer in contact with the third insulating film is a titanium film.
(12) The semiconductor integrated circuit device of the present invention includes the following steps.
(a) After forming a silicon oxide-based first insulating film on the main surface of the semiconductor substrate, a portion of the first insulating film on the first insulating film and in contact with the first insulating film is a high melting point metal except titanium, or titanium Depositing a conductive film made of an oxide of a high melting point metal, including
(b) forming a second insulating film on the upper portion of the wiring by forming a wiring extending at least a part thereof in contact with the first insulating film by patterning the conductive film;
(c) forming a capacitor having a capacitor insulating film composed of a first electrode, a dielectric film, and a second electrode on the second insulating film, wherein the capacitor forming step is performed to improve the film quality of the dielectric film. Heat treatment process.
(13) The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps.
(a) A MISFET for selecting memory cells constituting a memory cell of a DRAM is formed in a first region on a main surface of a semiconductor substrate, and a MISFET constituting a peripheral circuit of the DRAM is formed in a second region on a main surface of the semiconductor substrate. Process,
(b) forming a silicon oxide-based first insulating film on each of the memory cell selection MISFET and the peripheral circuit MISFET;
(c) a first contact hole is formed in the first insulating film on at least one of the source and the drain of the memory cell selection MISFET, and the first insulating film on each of the source and the drain of the MISFET of the peripheral circuit. Forming a second contact hole in the first circuit and forming a third contact hole in the first insulating film on the gate electrode of the MISFET of the peripheral circuit;
(d) the periphery exposed to the bottom of the second contact hole by depositing a titanium film in each of the second contact hole and the third contact hole and on top of the first insulating film, and then heat treating the semiconductor substrate. Forming a titanium silicide layer on each surface of a source and a drain of the MISFET of the circuit,
(e) after depositing a barrier metal film or a laminated film of a high melting point metal film excluding the barrier metal film and titanium on the titanium film including the inside of each of the second contact hole and the third contact hole, (1) forming a plug in each of the second contact hole and the third contact hole by removing the barrier metal film or the laminated film over the insulating film together with the titanium film;
(f) depositing a conductive film made of a high melting point metal other than titanium or a nitride of a high melting point metal, at least a portion of the first insulating film being in contact with the first insulating film;
(g) forming a bit line electrically connected to one of a source and a drain of the memory cell selection MISFET through the first contact hole by patterning the conductive film, and forming the second contact hole or the third contact. Forming a wiring of the first layer of the peripheral circuit electrically connected to the MISFET of the peripheral circuit through the hole;
(h) forming a capacitor for information storage composed of a first electrode, a dielectric film, and a second electrode on the second insulating film, wherein the process of forming the capacitor device is for improving the film quality of the dielectric film. Heat treatment process.
(14) In the method for manufacturing a semiconductor integrated circuit device of the present invention, in (13), the conductive film constituting each of the gate electrode of the MISFET for the memory cell selection and the gate electrode of the MISFET of the peripheral circuit is doped with impurities. It is a laminated film of a low resistance polycrystalline silicon film, a barrier metal film and a tungsten film.
(15) In the method for manufacturing a semiconductor integrated circuit device of the present invention, in (13), the wiring in the first layer of the bit line and the peripheral circuit is a tungsten film.
(16) In the method for manufacturing a semiconductor integrated circuit device of the present invention, in (13), the dielectric film is made of metal oxide.
(17) In the method for manufacturing a semiconductor integrated circuit device of the present invention, in (16), the metal oxide is tantalum oxide.
(18) In the method for manufacturing a semiconductor integrated circuit device of the present invention, in (13), the heat treatment temperature for improving the film quality of the high dielectric film is at least 750 占 폚.
(19) The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps.
(a) forming a memory cell selection MISFET constituting a memory cell of a DRAM in a first region on a main surface of a semiconductor substrate, and forming a MISFET constituting a peripheral circuit of the DRAM in a second region on a main surface of the semiconductor substrate; fair,
(b) forming a silicon oxide-based first insulating film on each of the memory cell selection MISFET and the peripheral circuit MISFET;
(c) A first contact hole is formed in the first insulating film on at least one of the source and the drain of the memory cell selection MISFET, and the first and second portions of the source and drain of the MISFET of the peripheral circuit are formed. Forming a second contact hole in the first insulating film, and forming a third contact hole in the first insulating film above the gate electrode of the MISFET of the peripheral circuit;
(d) depositing a cobalt film in each of the second contact hole and the third contact hole and an upper portion of the first insulating film, and then heat treating the semiconductor substrate to expose the bottom portion of the second contact hole. Forming a cobalt silicide layer on each surface of the source and drain of the MISFET of the peripheral circuit,
(e) after depositing a barrier metal film or a laminated film of a high melting point metal film excluding the barrier metal film and cobalt on an upper portion of the cobalt film including each of the second contact hole and the third contact hole, (1) forming a plug in each of the second contact hole and the third contact hole by removing the barrier metal film or the laminated film over the insulating film together with the cobalt film;
(f) depositing a conductive film made of a high melting point metal other than cobalt or a nitride of a high melting point metal, at least a portion of the first insulating film being in contact with the first insulating film;
(g) forming a bit line electrically connected to one of a source and a drain of the memory cell selection MISFET through the first contact hole by patterning the conductive film, and forming the second contact hole or the third contact. Forming a wiring of the first layer of the peripheral circuit electrically connected to the MISFET of the peripheral circuit through the hole;
(h) forming a capacitor for information storage composed of a first electrode, a dielectric film, and a second electrode on the second insulating film, wherein the process of forming the capacitor device is for improving the film quality of the dielectric film. Heat treatment process.
(Description of Preferred Embodiments)
EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing. In addition, in the whole figure for demonstrating embodiment, the same code | symbol is attached | subjected to the member which has the same function, and the repeated description is abbreviate | omitted.
1 is an overall plan view of a semiconductor chip on which a DRAM of the present embodiment is formed. As shown in the figure, a plurality of memory arrays are formed on the main surface of the semiconductor chip 1A made of single crystal silicon along the X direction (the long side direction of the semiconductor chip 1A) and the Y direction (the short side direction of the semiconductor chip 1A). (MARY) is arranged in a matrix. A sense amplifier SA is disposed between the memory arrays MARY adjacent to each other along the X direction. In the central portion of the main surface of the semiconductor chip 1A, control circuits such as a word driver WD, a data line selection circuit, an input / output circuit, a bonding pad, and the like are disposed.
2 is an equivalent circuit diagram of the DRAM. As shown, the memory array MARY of this DRAM includes a plurality of word lines WL (WLn-1, WLn, WLn + 1 ...) extending in the row direction and a plurality of word lines WLn extending in the column direction. Is composed of the bit lines BL and a plurality of memory cells MC arranged at their intersections. One memory cell that stores one bit of information is composed of one information storage capacitor element C and one memory cell selection MISFET Qs connected in series thereto. One of a source and a drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to the word driver WD, and one end of the bit line BL is connected to the sense amplifier SA.
3 is a sectional view of principal parts of a semiconductor substrate, each showing a portion of a DRAM memory array and a peripheral circuit; FIG. 4 is a schematic plan view of the semiconductor substrate showing a portion of a memory array. In addition, only the conductive layer (except the plate electrode) which comprises a memory cell is shown in FIG. 4, and the illustration of the insulating film between conductive layers or the wiring formed in the upper part of a memory cell is abbreviate | omitted.
As shown in FIG. 3, a DRAM memory cell is formed in a p-type well 2 formed on a main surface of a semiconductor substrate 1 made of p-type single crystal silicon. The p-type well 2 of the region where the memory cells are formed (memory array) has an n-type semiconductor region 3 formed thereunder to prevent noise from invading from an input / output circuit formed in another region of the semiconductor substrate 1 or the like. Is electrically separated from the semiconductor substrate 1.
The memory cell has a stacked structure in which the information storage capacitor C is disposed on the memory cell selection MISFET Qs. The memory cell selection MISFETs (Qs) are formed in an n-channel type and are formed in an active region L formed of an elongated island-shaped pattern extending straight along the X direction (column direction) as shown in FIG. have. In each of the active regions L, two memory cell selection MISFETs Qs sharing one of the source and the drain (n-type semiconductor region) are formed adjacent to each other in the X direction.
The element isolation region surrounding the active region L is composed of an element isolation groove 6 formed in the p-type well 2. The silicon oxide film 5 is embedded in the device isolation groove 6, and the surface thereof is planarized so as to have a height substantially equal to the surface of the active region L. Since the device isolation region formed by the device isolation groove 6 does not generate bird's beak at the end of the active region L, the device isolation region having the same dimension formed by the LOCOS (selective oxidation) method (field The effective area is larger than that of a field oxide film.
The memory cell selection MISFET Qs is mainly composed of the gate oxide film 7, the gate electrode 8A, and a pair of n-type semiconductor regions 9 and 9 constituting a source and a drain. The gate electrode 8A of the memory cell selection MISFET Qs is integrally formed with the word line WL, and extends linearly along the Y direction with the same width and the same space. The width of the gate electrode 8A (word line WL), that is, the gate length, and the spaces of two adjacent gate electrodes 8A (word line WL) are all determined by the resolution limit of photolithography. It is about the same as the machining dimension. The gate electrode 8A (word line WL) is a barrier metal layer made of, for example, a low resistance polycrystalline silicon film doped with n-type impurities such as P (phosphorus), and a WN (tungsten nitride) film formed thereon; And a polymetal structure composed of a high melting point metal film such as a W (tungsten) film formed thereon. Since the gate electrode 8A (word line WL) of the polymetal structure has lower electrical resistance than the gate electrode composed of a polycrystalline silicon film or a polyside film, the signal delay of the word line can be reduced.
The peripheral circuit of the DRAM is composed of an n-channel MISFET (Qn) and a p-channel MISFET (Qp). The n-channel MISFET Qn is formed in the p-type well 2, and is mainly formed in the pair of n + type semiconductor regions 10 and 10 constituting the gate oxide film 7, the gate electrode 8B, and the source and drain. It is composed by. Further, the p-channel MISFET Qp is formed in the n-type well 4 and mainly includes a pair of p + type semiconductor regions 11 constituting the gate oxide film 7, the gate electrode 8C, and the source and drain. 11). The gate electrodes 8B and 8C have the same polymetal structure as the gate electrode 8A (word line WL). The n-channel MISFET (Qn) and the p-channel MISFET (Qp) constituting the peripheral circuit are manufactured with a milder design rule than a memory cell.
The silicon nitride film 12 is formed on the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs, and the upper and sidewalls of the silicon nitride film 12 and the gate electrode ( A silicon nitride film 13 is formed on the sidewall of 8A (word line WL). Further, a silicon nitride film 12 is formed on each of the gate electrodes 8B and 8C of the MISFET of the peripheral circuit, and a silicon nitride film 13 is formed on each sidewall of the gate electrodes 8B and 8C. Side wall spacers 13s are formed.
The silicon nitride film 12 and the silicon nitride film 13 of the memory array are self-aligned on the source and drain (n-type semiconductor regions 9 and 9) of the memory cell selection MISFET Qs as described later. It is used as an etching stopper when forming contact holes with phosphorus (self-alignment). In addition, the sidewall spacer 13s of the peripheral circuit is used to make the source, the drain of the n-channel MISFET Qn, and the source, the drain of the p-channel MISFET Qp as a LDD (Lightly Doped Drain) structure.
An SOG film 16 is formed on each of the memory cell selection MISFETs (Qs), n-channel type MISFETs (Qn), and p-channel type MISFETs (Qp). Further, two layers of silicon oxide films 17 and 18 are formed further above the SOG film 16, and the upper surface of the silicon oxide film 18 is almost the same throughout the semiconductor substrate 1. It is planarized so that it may become height.
Contact holes penetrating through the silicon oxide films 18 and 17 and the SOG film 16 on the pair of n-type semiconductor regions 9 and 9 constituting the source and drain of the memory cell selection MISFET Qs. 19, 20) are formed. In the contact holes 19 and 20, a plug 21 made of a low-resistance polycrystalline silicon film doped with n-type impurities (for example, P (phosphorus)) is embedded.
The diameters of the bottom portions of the contact holes 19 and 20 in the X direction are different from those of the silicon nitride film 13 on one side wall of the two gate electrodes 8A (word lines WL) facing each other and the side walls on the other side. It is prescribed by the space of the silicon nitride film 13. That is, the contact holes 19 and 20 are formed in self-alignment with respect to the space of the gate electrode 8A (word line WL).
Of the pair of contact holes 19 and 20, the diameter of the contact hole 20 for connecting the information storage capacitor C is smaller than the dimension of the active direction L in the Y direction. On the other hand, the diameter of the contact hole 19 for connecting the bit line BL (the contact hole on the n-type semiconductor region 9 shared by the two memory cell selection MISFETs Qs) is the diameter in the Y direction. It is larger than the dimension of the active direction L of the Y direction. That is, the contact hole 19 is constituted by a substantially rectangular planar pattern whose diameter in the Y direction is larger than the diameter in the X direction (upper end), and part of the contact hole 19 is separated from the active region L on the element isolation groove 6. Extends to. By forming the contact holes 19 in such a pattern, when the bit lines BL and the n-type semiconductor region 9 are electrically connected through the contact holes 19, the width of the bit lines BL is partially reduced. The memory cell size can be reduced since it is not necessary to increase the size of the active region L to the upper portion of the active region L or extend the portion of the active region L in the bit line BL direction.
The silicon oxide film 28 is formed on the silicon oxide film 18. Through-holes 22 are formed in the silicon oxide film 28 on the upper side of the contact hole 19, and therein, a plug 35 made of a conductive film in which Ti films, TiN films, and W films are sequentially stacked from the lower layer is formed. Buried In addition, at the interface between the plug 35 and the plug 21 embedded in the contact hole 19 in the lower portion of the through hole 22, the Ti film constituting a part of the plug 35 and the plug 21 are formed. The TiSi ₂ (titanium silicide) layer 37 formed by the reaction with the polycrystalline silicon film is formed. The through hole 22 is disposed above the element isolation groove 6 deviating from the active region L. As shown in FIG.
The bit line BL is formed on the silicon oxide film 28. The bit line BL is disposed above the element isolation groove 6 and extends linearly along the X direction with the same width and the same space. The bit line BL is formed of a W film, and includes a through hole 22 formed in the silicon oxide film 28 and an insulating film (silicon oxide films 28, 18, 17, SOG film 16, and gate) below the bit line BL. The n-type semiconductor region 9 shared by one (two memory cell selection MISFETs Qs) of the source and drain of the memory cell selection MISFETs Qs through the contact hole 19 formed in the oxide film 7. ) Is electrically connected. Further, the bit line BL is made as wide as possible to reduce the parasitic capacitance formed between the adjacent bit lines BL as much as possible.
Even when the memory cell size is reduced by increasing the space of the bit line BL to reduce the parasitic capacitance, the signal voltage at the time of reading the charge (information) accumulated in the information storage capacitor C is large. can do. In addition, the space of the bit line BL is increased, whereby a through hole (through hole for connecting the information storage capacitor C and the contact hole 20 formed in the space region of the bit line BL to be described later). Since the opening margin of the 48 can be sufficiently secured, a short circuit between the bit line BL and the through hole 48 can be reliably prevented even when the memory cell size is reduced. .
In addition, by configuring the bit line BL from the metal W, the sheet resistance is 2 / Since it can be reduced to an extent, information reading and writing can be performed at high speed. In addition, since the bit lines BL and the wirings 23 to 26 of the peripheral circuit described later can be simultaneously formed in the same process, the DRAM manufacturing process can be simplified. In addition, since the bit line BL is made of a metal W having high heat resistance and electromigration resistance, disconnection can be reliably prevented even when the width of the bit line BL is reduced.
The wirings 23 to 26 of the first layer are formed on the silicon oxide film 28 of the peripheral circuit. These wirings 23 to 26 are made of the same conductive material W as the bit lines BL, and are simultaneously formed in the process of forming the bit lines BL as described later. The wirings 23 to 26 are MISFETs (n-channel MISFETs (Qn) and p-channels) of peripheral circuits through the contact holes 30 to 34 formed in the silicon oxide films 28, 18, and 17 and the SOG film 16. It is electrically connected to the type MISFET (Qp).
In the contact holes 30 to 34 connecting the MISFET of the peripheral circuit and the wirings 23 to 26, a plug 35 made of a conductive film in which a Ti film, a TiN film, and a W film are sequentially stacked from the lower layer is embedded. The contact holes 30 to 34 formed above the source and drain (n + type semiconductor region 10 and p + type semiconductor region 11) of the MISFET of the peripheral circuit among these contact holes 30 to 34. At the bottom, a TiSi ₂ layer 37 formed by the reaction between the Ti film constituting a part of the plug 35 and the semiconductor substrate 1 (Si) is formed, whereby the plug 35 and the source, The contact resistance with the drain (n + type semiconductor region 10 and p + type semiconductor region 11) is reduced.
A silicon oxide film 38 is formed on each of the bit lines BL and the wirings 23 to 26 of the first layer, and an SOG film 39 is formed further on the silicon oxide film 38. have. The SOG film 39 is planarized so that the surface thereof becomes almost the same height in the whole area | region of the semiconductor substrate 1.
The silicon nitride film 44 is formed on the SOG film 39 of the memory array, and the information storage capacitor C is further formed on the silicon nitride 44. The information storage capacitor C is constituted by a lower electrode (accumulation electrode) 45 and an upper electrode (plate electrode) 47 and a Ta ₂ O ₅ (tantalum oxide) film 46 provided therebetween. have. The lower electrode 45 is made of, for example, a low resistance polycrystalline silicon film doped with P (phosphorus), and the upper electrode 47 is made of, for example, a TiN film.
The lower electrode 45 of the information storage capacitor C is configured in an elongated pattern extending straight along the X direction in FIG. 4. The lower electrode 45 is connected to a contact hole through a plug 49 embedded in a through hole 48 penetrating through the silicon nitride film 44, the SOG film 39, and the silicon oxide films 38 and 28 below. 20 is electrically connected to the plug 21 in the circuit, and is electrically connected to the other (n-type semiconductor region 9) of the source and drain of the memory cell selection MISFET Qs through the plug 21. have. The through hole 48 formed between the lower electrode 45 and the contact hole 20 has a diameter smaller than the minimum machining dimension in order to reliably prevent a short circuit between the bit line BL or the plug 35 thereunder. 0.14 µm), for example. The plug 49 embedded in the through hole 48 is made of, for example, a low resistance polycrystalline silicon film doped with P (phosphorus).
On the SOG film 39 of the peripheral circuit, a silicon oxide film 50 having a thick film thickness almost the same as that of the lower electrode 45 of the information storage capacitor C is formed. By forming the silicon oxide film 50 of the peripheral circuit with such a thick film thickness, the surface of the interlayer insulating film 56 formed on the information storage capacitor C has almost the same height in the memory array and the peripheral circuit. do.
The interlayer insulating film 56 is formed on the information storage capacitor C, and the wirings 52 and 53 of the second layer are formed thereon. The interlayer insulating film 56 is made of a silicon oxide film, and the wirings 52 and 53 of the second layer are made of a conductive film mainly composed of Al (aluminum). The second wiring 53 formed in the peripheral circuit has a through hole 54 formed in the lower insulating film (interlayer insulating film 56, silicon oxide film 50, SOG film 39, and silicon oxide film 38). Is electrically connected to the wiring 26 of the first layer. Inside the through hole 54, a plug 55 made of, for example, a Ti film, a TiN film, and a W film is embedded.
A second interlayer insulating film 63 is formed above the wirings 52, 53 of the second layer, and wirings 57, 58, 59 of the third layer are formed thereon. The interlayer insulating film 63 is composed of a silicon oxide insulating film (for example, a three-layer insulating film consisting of a silicon oxide film, an SOG film, and a silicon oxide film), and the wirings 57, 58, and 59 of the third layer are formed of a second layer. It is the same as the wiring 52 and 53 of a layer, and is comprised from the electrically conductive film which mainly uses Al.
The wiring 58 of the third layer is electrically connected to the upper electrode 47 of the data storage capacitor C through the through holes 60 formed in the interlayer insulating films 63 and 56 of the lower layer. The wiring 59 of the third layer of the peripheral circuit is electrically connected to the wiring 53 of the second layer through the through hole 61 formed in the interlayer insulating film 63 of the lower layer. In the through holes 60 and 61, a plug 62 made of, for example, a Ti film, a TiN film, and a W film is embedded.
Next, an example of the DRAM manufacturing method configured as described above will be described in the order of the process using FIGS. 5 to 38.
First, as shown in FIG. 5, the element isolation groove 6 is formed in the element isolation region of the main surface of the semiconductor substrate 1 made of single crystal silicon having a p-resistance of about 10 Cm. The device isolation groove 6 etches the surface of the semiconductor substrate 1 to form a groove having a depth of about 300 to 400 nm, and then silicon oxide is deposited on the semiconductor substrate 1 including the inside of the groove by CVD. After the film 5 is deposited, the silicon oxide film 5 is formed by polishing back by chemical mechanical polishing (CMP) method.
Next, as shown in FIG. 6, n-type impurities such as P (phosphorus) are ion-implanted into the semiconductor substrate 1 in the region (memory array) in which the memory cells are formed, thereby forming the n-type semiconductor region 3. Then, p-type impurities such as B (boron) are ion-implanted into the memory array and a part of the peripheral circuit (region forming the n-channel MISFET (Qn)) to form the p-type well 2, and the other part of the peripheral circuit. An n-type impurity, such as P (phosphorus), is ion-implanted into a portion (region forming the p-channel MISFET Qp) to form the n-type well 4.
Subsequently, impurities for adjusting the threshold voltage of the MISFET, such as BF ₂ (boron fluoride), are ion-implanted into the p-type well 2 and the n-type well 4, and then the p-type well 2 and the n-type After washing each surface of the well 4 with a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet oxidized to the respective surfaces of the p-type well 2 and the n-type well 4. A clean gate oxide film 7 having a film thickness of about 7 nm is formed.
Next, as shown in FIG. 7, the gate electrode 8A (word line WL) and the gate electrodes 8B and 8C are formed on the gate oxide film 7. The gate electrode 8A (word line WL) and the gate electrodes 8B and 8C have a polycrystalline silicon film having a thickness of about 70 nm, for example, doped with n-type impurities such as P (phosphorus) on the semiconductor substrate 1. Was deposited by CVD, and then a WN (tungsten nitride) film having a thickness of about 5 nm and a W film having a thickness of about 100 nm were deposited by sputtering thereon, and then 200 nm thick thereon. The silicon nitride film 12 of a degree is deposited by CVD, and then formed by patterning these films using a photoresist film as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting at high temperature heat treatment to form a high resistance silicide layer at both interfaces. As the barrier layer, a WN film high melting point metal nitride film such as a TiN (titanium nitride) film may be used. The gate electrode 8A (word line WL) of the memory cell selection MISFET Qs is formed using, for example, an exposure technique using a KrF excimer laser having a wavelength of 248 nm as a light source and a phase shifter technique.
Next, as shown in FIG. 8, p-type impurities, such as B (boron), are ion-implanted into the n-type well 4, and the p-type semiconductor region (i) is formed in the n-type wells 4 on both sides of the gate electrode 8C. 15). In addition, n-type impurities such as P (phosphorus) are ion-implanted into the p-type well 2 to form the n-type semiconductor region 9a in the p-type wells 2 on both sides of the gate electrode 8A. The n-type semiconductor region 14 is formed in the p-type wells 2 on both sides of the electrode 8B. By the processes thus far, the MISFETs (Qs) for selecting memory cells are almost completed.
Next, as shown in FIG. 9, after depositing the silicon nitride film 13 of about 50 nm in thickness by the CVD method on the semiconductor substrate 1, the silicon nitride film 13 of a memory array is made into the photoresist film. The sidewall spacers 13s are formed on the sidewalls of the gate electrodes 8B and 8C of the peripheral circuit by anisotropically etching the silicon nitride film 13 of the peripheral circuit. This etching is performed using a gas that etches the silicon nitride film 13 at a high selectivity in order to minimize the amount of cut between the silicon oxide film 5 and the gate oxide film 7 embedded in the device isolation groove 6. In addition, in order to minimize the amount of cut in the silicon nitride film 12 on the gate electrodes 8B and 8C, the amount of overetching is limited to the required minimum amount.
Next, as shown in FIG. 10, p-type impurities, such as B (boron), are ion-implanted into the n-type well 4 of the peripheral circuit to form the p + type semiconductor region 11 (source, of the p-channel MISFET Qp). Drain) and ion implantation of n-type impurities, such as As (arsenic), into the p-type wells 2 of the peripheral circuit to form the n + -type semiconductor region 10 (source, drain) of the n-channel MISFET Qn. Form. By the steps up to this point, the p-channel MISFET (Qp) and the n-channel MISFET (Qn) having the LDD structure are almost completed.
Next, as shown in FIG. 11, after spin-coating the SOG film | membrane 16 of the film thickness about 300 nm on the semiconductor substrate 1, and performing baking process in the oxygen atmosphere about 400 degreeC containing water vapor, Further, the SOG film 16 is densified (densified) by heat treatment at 800 ° C. for about 1 minute. As the SOG film 16, for example, polysilazan-based inorganic SOG is used.
The SOG film 16 has a higher reflow property than a glass flow film such as a BPSG film, and has a fine gap fill property. Therefore, the SOG film 16 has a finer gate electrode that has been refined to a resolution resolution of photolithography. A void does not occur even if it fills in the space of 8A) (word line WL). In addition, since the SOG film 16 has high reflowability even without performing the high temperature and long heat treatment required for the BPSG film or the like, the MISFET (n channel) of the source, drain or peripheral circuit of the memory cell selection MISFET (Qs) is obtained. The thermal diffusion of impurities injected into the source and drain of the type MISFET (Qn) and the p-channel type MISFET (Qp) can be suppressed to achieve a shallow junction, and at the same time, the gate electrode 8A (word line ( WL)) and the metal (W film) constituting the gate electrodes 8B and 8C can be suppressed from oxidizing, so that high performance of the memory cell selection MISFET Qs and the peripheral circuit MISFET can be realized.
Next, as shown in FIG. 12, a silicon oxide film 17 having a thickness of about 600 nm is deposited on the SOG film 16, and the silicon oxide film 17 is then polished by a CMP method. After the surface is planarized, a silicon oxide film 18 having a film thickness of about 100 nm is deposited thereon. The upper silicon oxide film 18 is deposited in order to repair fine scratches on the surface of the lower silicon oxide film 17 generated when the CMP method is polished.
Next, as shown in FIG. 13, silicon oxide in the upper portion of the n-type semiconductor region (source, drain) 9a of the memory cell selection MISFET Qs by dry etching using the photoresist film 27 as a mask. The membranes 18 and 17 are removed. This etching is performed using a gas for etching the silicon oxide film 17 at a high selectivity in order to prevent the silicon nitride film 13 under the silicon oxide film 17 from being removed.
14, the silicon nitride film 13 on the upper portion of the n-type semiconductor region (source, drain) 9a is removed by dry etching using the photoresist film 27 as a mask. By removing the lower gate oxide film 7 below, a contact hole 19 is formed in one upper portion of the n-type semiconductor region (source and drain) 9a, and the contact hole 20 is disposed in the upper portion of the other layer. ).
The etching of the silicon nitride film 13 is performed using a gas for etching the silicon nitride film 13 at a high selectivity in order to minimize the amount of cut in the semiconductor substrate 1 or the device isolation groove 6. This etching is performed under conditions such as anisotropically etching the silicon nitride film 13, and the silicon nitride film 13 is left on the sidewall of the gate electrode 8A (word line WL). As a result, minute contact holes 19 and 20 whose diameters in the bottom portion (diameter in the X direction) are less than or equal to the resolution limit of photolithography can be formed in self-alignment with respect to the space of the gate electrode 8A (word line WL). Can be.
Next, after the photoresist film 27 is removed, the semiconductor substrate 1 exposed to the bottoms of the contact holes 19 and 20 using an etching solution of hydrofluoric acid (eg, hydrofluoric acid + ammonium fluoride mixture). ) Surface is cleaned and dry etching residue, photoresist residue and the like are removed. At this time, the SOG film 16 exposed on the sidewalls of the contact holes 19 and 20 is also exposed to the etchant, but the SOG film 16 densified (densified) at a high temperature of about 800 ° C. does not perform this densify treatment. Compared to the film, the hydrofluoric acid system has a higher resistance to the etching solution, so that the sidewalls of the contact holes 19 and 20 are not significantly undercut by this wet etching process. This can reliably prevent a short circuit between the plugs 21 embedded in the contact holes 19 and 20 in the next step.
Further, after forming the contact holes 19 and 20, n-type impurities (for example, phosphorus) are ion-implanted into the p-type wells 2 through the contact holes 19 and 20, thereby selecting MISFETs for memory cell selection (Qs). The n-type semiconductor layer may be formed in the p-type well 2 in a region deeper than the source and the drain of the (). Since the n-type semiconductor layer has an effect of relaxing an electric field concentrated at the ends of the source and the drain, it is possible to reduce the leakage current at the ends of the source and the drain, thereby improving the refresh characteristics of the memory cell.
Next, as shown in FIG. 15, the plug 21 is formed in the contact holes 19 and 20. The plug 21 deposits a polycrystalline silicon film having a thickness of about 300 nm on the silicon oxide film 18 doped with n-type impurities (for example, As) by CVD, and then deposits the polycrystalline silicon film on the CMP method. It forms by grinding | polishing to the inside of the contact hole 19,20.
Subsequently, a silicon oxide film 28 having a thickness of about 200 nm is deposited on the silicon oxide film 18 by CVD, followed by heat treatment at 800 ° C. for about 1 minute in a nitrogen gas atmosphere. By this heat treatment, the n-type impurities in the polycrystalline silicon film constituting the plug 21 diffuse from the bottom of the contact holes 19 and 20 to the n-type semiconductor region 9a of the MISFET Qs for memory cell selection, A low resistance n-type semiconductor region (source, drain) 9 is formed.
Next, as shown in FIG. 16, the through-hole 22 is formed by removing the silicon oxide film 28 of the upper part of the contact hole 19 by dry etching using the photoresist film as a mask. This through hole 22 is disposed above the element isolation groove 6 deviating from the active region L. As shown in FIG.
Subsequently, the silicon oxide films 28, 18 and 17, the SOG film 16 and the gate oxide film 7 of the peripheral circuit are removed by dry etching using the photoresist film as a mask, whereby n ⁺ of the n-channel MISFET Qn is removed. Contact holes 30 and 31 are formed in the upper portion of the type semiconductor region 10 (source and drain), and contacts are formed in the upper portion of the p ⁺ type semiconductor region 11 (source and drain) of the P-channel MISFET Qp. The holes 32 and 33 are formed. At this time, a contact hole 34 is formed on the gate electrode 8C of the P-channel MISFET Qp at the same time, and a contact hole not shown on the gate electrode 8B of the n-channel MISFET Qn is shown. To form.
As described above, the etching to form the through holes 22 and the etching to form the contact holes 30 to 34 are performed in separate processes, thereby forming the deep contact holes 30 to 34 of the peripheral circuit. The problem that the plug 21 exposed to the bottom of the shallow through hole 22 of the array is deeply cut can be prevented. The through hole 22 and the contact holes 30 to 34 may be formed in the reverse order.
Next, as shown in FIG. 17, Ti film 36 having a film thickness of about 40 nm is deposited on the silicon oxide film 28 including the contact holes 30 to 34 and the inside of the through hole 22. . The Ti film 36 is deposited at the bottom of the contact holes 30 to 34 having a large aspect ratio by using a highly-oriented sputtering method such as a collimation sputter that can secure a film thickness of about 10 nm or more.
Subsequently, heat treatment is performed at about 650 ° C. for about 30 seconds in an Ar (argon) gas atmosphere without exposing the Ti film 36 to the atmosphere, and at about 750 ° C. for about 1 minute in a nitrogen gas atmosphere. As a result of this heat treatment, as shown in Fig. 18, the Si substrate at the bottom of the contact holes 30 to 33 and the Ti film 36 react, and the n ⁺ type semiconductor region 10 of the n channel type MISFET Qn ( A TiSi ₂ layer 37 having a film thickness of about 10 nm is formed on the surface of the source and the drain) and the surface of the p ⁺ type semiconductor region 11 (the source and the drain) of the p-channel MISFET Qp. In addition, the surface of the thin Ti film 36 deposited on the sidewalls of the contact holes 30 to 34 is oxidized by the heat treatment in the nitrogen gas atmosphere, resulting in a stable film that is difficult to react with Si.
At this time, the surface of the Ti film 36 above the silicon oxide film 28 is also nitrided, but portions other than the surface remain unreacted without being nitrided. The TiSi ₂ layer 37 is formed on the surface of the plug 21 at the bottom of the through hole 22 by the reaction between the polycrystalline silicon film constituting the plug 21 and the Ti film 36. By forming the TiSi ₂ layer 37 at the bottom of the contact holes 30 to 33, the plug 35 formed in the contact holes 30 to 33 in the next step, and the source and drain of the MISFET of the peripheral circuit ( Since the contact resistance of the portion where the n ⁺ type semiconductor region 10 and the P ⁺ type semiconductor region 11 are in contact with each other can be reduced to 1 KΩ or less, the peripheral circuits such as the sense amplifier SA and the word driver WD can be reduced. High speed operation is possible. The silicide layer at the bottom of the contact holes 30 to 33 may be made of a high melting point metal silicide other than TiSi ₂ , such as CoSi ₂ (cobalt silicide), TaSi ₂ (tantal silicide), MoSi ₂ (molybdenum silicide), or the like. Do.
Next, as shown in FIG. 19, the TiN film 40 of about 30 nm in thickness is deposited on the Ti film 36 by CVD method. Since the CVD method has better step coverage than the sputtering method, the TiN film 40 having the same thickness as the flat portion can be deposited on the bottom of the contact holes 30 to 34 having a large aspect ratio. have. Subsequently, a thick W film 41 having a thickness of about 300 nm was deposited on the TiN film 40 by CVD using tungsten hexafluoride (WF ₆ ), hydrogen, and monosilane (SiH ₄ ) as the source gas. The inside of each of the contact holes 30 to 34 and the through hole 22 is completely filled with the W film 41.
In addition, if the unreacted Ti film 36 is removed with an etching solution immediately after the TiSi ₂ layer 37 is formed, the contact hole 34 formed on the gate electrode 8C of the P-channel MISFET Qp is formed. An etchant penetrates into the inside of a contact hole (not shown) formed inside or above the gate electrode 8B of the n-channel MISFET Qn, so that the surface (W film) of the gate electrodes 8B and 8C having a polymetal structure is formed. It is etched. In order to prevent this, in the present embodiment, after the TiSi ₂ layer 37 is formed at the bottom of the contact holes 30 to 33, the silicon oxide film 28 is formed in the upper portion of the contact hole 30 to 34. The TiN film 40 and the W film 41 are deposited on top of the remaining unreacted Ti film 36.
Next, as shown in Fig. 20, the W film 41, the TiN film 40 and the Ti film 36 on the silicon oxide film 28 are removed (polished back) using the CMP method. A plug 35 composed of the W film 41, the TiN film 40, and the Ti film 36 is formed in each of the holes 30 to 34 and the through hole 22. The plug 35 may be formed by removing (etching back) the W film 41, the TiN film 40, and the Ti film 36 on the silicon oxide film 28 by dry etching. At this time, if the removal of the Ti film 36 on the silicon oxide film 28 is insufficient, a part of the wirings 23 to 26 formed on the silicon oxide film 28 in the next step are oxidized at a later high temperature heat treatment. Care should be taken because peeling may occur from the surface of the silicon film 28.
Since the plug 35 is mainly composed of the W film 41, which is a high melting point metal, the resistance is low and the heat resistance is high. Further, in the TiN film 40 formed under the W film 41, the tungsten hexafluoride and Si react with each other when the W film 41 is deposited by CVD, resulting in defects (encroachment or wormholes). wormholes)) and also serves as a barrier layer for preventing the W film 41 and the Si substrate from reacting (silicide reaction) in a later high temperature heat treatment step. As the barrier layer, a high melting point metal nitride (for example, a WN film) other than TiN may be used.
The plug 35 may be configured mainly using the TiN film 40 without using the W film 41. That is, the plug 35 may be formed by embedding the thick film thickness TiN film 40 in each of the contact holes 30 to 34 and the through hole 22. In this case, the resistance of the plug 35 is higher than in the case where the W film 41 is mainly composed, but the W film 42 deposited on the silicon oxide film 28 in the following step is dried. When forming the bit lines BL and the wirings 23 to 26 of the first layer of the peripheral circuit, the TiN film 40 serves as an etching stopper, so that the wirings 23 to 26 and the contact holes 30 to 34 are formed. The poor installation margin is greatly improved, and the degree of freedom in layout of the wirings 23 to 26 is greatly improved.
Next, the bit lines BL and the wirings 23 to 26 of the first layer of the peripheral circuit are formed on the silicon oxide film 28 in the following manner.
First, as shown in FIG. 21, the surface of the silicon oxide film 28 is wet-washed to sufficiently remove the polishing residue, and then a W film 42 having a thickness of about 100 nm is deposited on the upper portion by sputtering. Next, as shown in FIG. 22, by dry etching the W film 42 using the photoresist film 43 formed on the W film 42 as a mask, the bit lines BL and the peripheral circuits. The wirings 23 to 26 of the first layer of the film are formed. In addition, since the W film 42 has a high light reflectance, the photoresist film 43 may cause a halation during exposure, thereby reducing the dimensional accuracy of the pattern (width and space). In order to prevent this, the photoresist film 43 may be applied after thinly depositing an anti-reflection film on the W film 42. As the antireflection film, an organic material or a metal material having a low light reflectance (for example, a TiN film) is used.
Here, the result of having examined the adhesiveness of a silicon oxide film and the various metal films deposited on it is demonstrated.
TABLE 1
Sample NumberWayInterface situationRemarks OneW / TiN / TiPeeling Occurrence2W / TiN / TiNxPeeling OccurrenceX = 10% 3W / TiN / TiNxPeeling OccurrenceX = 15% 4W / TiN / TiNxPeeling OccurrenceX = 20% 5W / TiNNo peeling6WNo peeling
Note 1) After annealing for 5 minutes at 800 ° C
Note 2) Plasma CVD-SiO ₂ on base and W
In Table 1, six kinds of metal films (samples 1 to 6) were deposited on the surface of the silicon oxide film deposited by plasma CVD, and heat-treated in a nitrogen atmosphere at 800 ° C. for 5 minutes. It is summarized. In the entire sample, the W film was deposited by sputtering, and the film thickness was 300 nm. The TiN films of Samples 1 to 5 were all deposited by the reactive sputtering method, and the film thickness was 50 nm. The TiNx films of Samples 2, 3 and 4 were deposited by varying the composition ratio (x) by the reactive sputtering method. Specifically, the composition ratio (x) was changed by adjusting the nitrogen partial pressure of Ar (argon) -nitrogen mixed gas. The Ti film of Sample 1 was deposited by sputtering, and the film thickness was 50 nm.
As shown in the table, peeling occurred at the interfaces of Samples 1 to 4, but peeling of Samples 5 and 6 did not occur at all. From this, it was found that peeling of the film occurred when the high temperature heat treatment was performed while the Ti compound film and the silicon oxide film contained in an excessive amount of the Ti film were in contact with the interface. Therefore, in view of the thermochemical generated energy for producing an oxide, it is an energy change in which the Si side tends to form oxides more easily than W and the Ti side tends to form oxides more than Si. Therefore, it is presumed that the property of this material is the cause of the peeling of the film described above. In addition, even when Ti is present at the interface, when it is present as a stable nitrogen compound (TiN) and not as a Ti single substance, energy for breaking Ti-N bonds is required, and this does not cause peeling of the film in the sample (5). It seems to be the cause.
In the through hole 22 and the contact holes 30 to 34, the sidewalls remain in contact with the Ti film 22, but the plug electrodes of the through hole 22 and the contact holes 30 to 34 are formed. Since the 35 is bonded to the lower polycrystalline silicon plug 21 or the semiconductor substrate, the bit line BL or the wirings 23 to 26 are present in the upper layer of the plug electrode 35, which is not a problem.
In the above-described manufacturing method, the W film 41, the TiN film 40, and the Ti film 36 on the upper portion of the silicon oxide film 28 are removed once, and the inside of the contact holes 30 to 34 and the through hole 22 are removed. After the plug 35 is formed inside the W 35, a newly deposited W film 42 is patterned on the silicon oxide film 28 to form the bit lines BL and the wirings 23 to 26. Therefore, according to this method, the manufacturing process is increased as compared with the case of forming the bit lines BL and the wirings 23 to 26 by patterning the W film 41, the TiN film 40, and the Ti film 36. The defect that causes the bit line BL or the wirings 23 to 26 to peel off by the high temperature heat treatment performed later when the information storage capacitor C is formed on the bit line BL can be reliably prevented. Can be.
In addition, after the plug 35 is formed in the contact holes 30 to 34 having a large aspect ratio, the silicon oxide film is formed into the W film 42 for forming the bit lines BL and the wirings 23 to 26. According to the above-described manufacturing method deposited on top of (28), it is not necessary to consider embedding of the film into the through hole 22 and the contact holes 30 to 34 when the W film 42 is deposited. The film 42 can be deposited to a thin film thickness. That is, according to this manufacturing method, since the film thickness of the bit line BL can be made thin, the parasitic capacitance formed between adjacent bit lines BL can be further reduced.
In addition, the surface of the silicon oxide film 28 is polished and planarized by a CMP method, and the over-etching amount at the time of etching the W film 42 is deposited by depositing a W film 42 having a thin film thickness on the top. Since it can reduce, the problem that the plug 35 inside the through hole 22 which has a diameter larger than the width of the photoresist film 43 is cut deep can be prevented.
The bit lines BL and the wirings 23 to 26 may be formed using a W film deposited by a CVD method or a laminated film of a W film and a TiN film. Further, other high melting point metals (such as Mo films and Ta films) having good adhesion to the silicon oxide insulating film, a single layer film of nitride thereof, or a laminated film thereof may be formed.
Next, as shown in FIG. 23, a silicon oxide film 38 having a thickness of about 100 nm is deposited on each of the bit lines BL and the wirings 23 to 26 of the first layer, and then a silicon oxide film ( After the spin coating of the SOG film 39 having a thickness of about 250 nm on the upper part of the layer 38), baking is performed in an oxygen atmosphere of about 400 ° C. containing water vapor, followed by heat treatment at about 800 ° C. for about 1 minute. By densification, the surface of the SOG film 39 is planarized.
As described above, the surface of the silicon oxide film 28 is flattened, and a thin film thickness W film 39 is deposited thereon to form the bit lines BL and the wirings 23 to 26 of the first layer. As a result, the base step difference of the SOG film 39 can be reduced, so that the upper portions of the bit lines BL and the wirings 23 to 26 are each formed of two layers of insulating films (silicon oxide film 38 and SOG film 39). You can flatten only with)). That is, even when the top of the gate electrodes 8A, 8B, and 8C are planarized, even if the silicon oxide film 17 is deposited on the SOG film 16 and the surface thereof is not polished by the CMP method, sufficient flatness is achieved. Since it can ensure, a manufacturing process can be shortened.
In addition, when the step difference between the bit lines BL and the wirings 23 to 26 of the first layer is small, planarization can be achieved by simply depositing the silicon oxide film 38 without using the SOG film 39. Can be. On the other hand, when the density difference between the bit lines BL and the wirings 23 to 26 is large and sufficient flatness cannot be obtained only by the SOG film 39, the surface of the SOG film 39 is polished by the CMP method. A silicon oxide film may be deposited on the upper portion of the SOG film 39 to repair fine polishing defects on the surface. When the temperature for densifying the SOG film 39 cannot be made too high, a silicon oxide film may be further deposited on top of it to compensate for the decrease in moisture resistance.
Next, as shown in FIG. 24, a polycrystalline silicon film 70 having a thickness of about 200 nm is deposited on the SOG film 39 by CVD, and then the polycrystalline silicon film 70 using the photoresist film as a mask. Dry etching is performed to form the through hole 71 above the contact hole 20. This through hole 71 is formed such that its diameter is about the same as the minimum machining dimension.
Next, as shown in FIG. 25, the sidewall spacer 72 made of a polycrystalline silicon film is formed on the sidewall of the through hole 71. The sidewall spacer 72 deposits a second polycrystalline silicon film (not shown) having a thickness of about 60 nm on the upper portion of the polycrystalline silicon film 70 including the inside of the through hole 71 by CVD. The polycrystalline silicon film is etched and left on the sidewall of the through hole 71. By forming this sidewall spacer 72, the inner diameter (inner diameter) of the through hole 71 becomes finer than the minimum machining dimension.
Next, as shown in FIG. 26, the insulating film (SOG film 39) and the silicon oxide films 38 and 28 at the bottom of the through hole 71 using the polycrystalline silicon film 70 and the sidewall spacer 72 as a mask. ), The through hole 48 reaching the contact hole 20 is formed through the space region between the bit line BL and the bit line BL adjacent thereto.
Since the through hole 48 is formed using the sidewall spacer 72 of the side wall of the through hole 71 having a smaller inner diameter than the minimum machining dimension, the inner diameter becomes smaller than the minimum machining dimension. Since the space area of the bit line BL and the installation margin of the through hole 48 can be sufficiently secured by this, the plug 49 embedded in the inside of the through hole 48 in the following process is formed by the bit line BL. Or short circuit with the plug 35 at the bottom thereof can be prevented.
Next, as shown in FIG. 27, a polycrystalline silicon film having a film thickness of about 200 nm which is doped with an n-type impurity (for example, P (phosphorus)) on the polycrystalline silicon film 70 including the inside of the through hole 48 ( After depositing the polycrystalline silicon film together with the polycrystalline silicon film 70 and the sidewall spacer 72 by depositing a CVD method (not shown). 49).
Next, as shown in FIG. 28, a silicon nitride film 44 having a thickness of about 200 nm is deposited on the top of the SOG film 39 by CVD, and then nitrided in the peripheral circuit by dry etching using the photoresist film as a mask. The silicon film 44 is removed. The silicon nitride film 44 remaining in the memory array is used as an etching stopper when etching the silicon oxide film in the step of forming the lower electrode 45 of the information storage capacitor C described later.
Next, as shown in FIG. 29, the silicon oxide film 50 is deposited on the silicon nitride film 44 by the CVD method, and then the silicon oxide film 50 and the silicon nitride below the photoresist film are used as a mask. The dry etching of the film 44 forms a recess 73 in the upper portion of the through hole 48. Since the lower electrode 45 of the information storage capacitor C is formed along the inner wall of the concave groove 73, in order to increase the surface charge of the lower electrode 45 to increase the accumulated charge amount, the silicon oxide film 50 It is necessary to deposit to a thick film thickness (for example, about 1.3 mu m).
Next, as shown in FIG. 30, the polycrystalline silicon film of about 60 nm in thickness which doped n type impurity (for example, P (phosphorus)) in the upper part of the silicon oxide film 50 containing the inside of the recessed groove 73. Then, as shown in FIG. 45A is deposited by the CVD method. This polycrystalline silicon film 45A is used as the lower electrode material of the information storage capacitor C.
Next, as shown in FIG. 31, the SOG film 74 of about 300 nm in thickness is spin-coated on the polycrystalline silicon film 45A including the inside of the recessed groove 73, and then about 400 degreeC. After the heat treatment is performed to bake the SOG film 74, the SOG film 74 outside the recessed groove 73 is etched and removed.
32, the upper portion of the polycrystalline silicon film 45A of the peripheral circuit is covered with the photoresist film 75, and the polycrystalline silicon film 45A on the upper portion of the silicon oxide film 50 of the memory array is covered. By removing by etching (anisotropic etching), the lower electrode 45 is formed along the inner wall of the concave groove 73. The lower electrode 45 may be formed of a conductive film other than the polycrystalline silicon film 45A. The conductive film for the lower electrode is a conductive material having heat resistance and oxidation resistance such that it is not degraded by the high temperature heat treatment of the capacitive insulating film performed in the following process, for example, a high melting point metal such as W, Ru (ruthenium), RuO ( It is preferable to comprise with conductive metal oxides, such as ruthenium oxide) and IrO (iridium oxide).
33, the silicon oxide film 50 remaining in the gap between the recessed groove 73 and the recessed groove 73 and the SOG film 74 inside the recessed groove 73 are fluorinated. The photoresist film 75 is removed after simultaneous removal with a hydrogen acid etching solution. Subsequently, the cylindrical lower electrode 45 is completed by removing the polycrystalline silicon film 45A in the peripheral circuit by dry etching using the photoresist film covering the memory array as a mask. Since the silicon nitride film 44 is formed at the bottom of the silicon oxide film 50 in the gap between the concave grooves, the SOG film 39 in the lower layer is not etched when the silicon oxide film 50 is wet etched. At this time, since the surface of the peripheral circuit is covered with the polycrystalline silicon film 45A, the thick silicon oxide film 50 in the lower layer is not etched.
By leaving the thick silicon oxide film 50 in the peripheral circuit, the surfaces of the interlayer insulating films 56 and 63 formed on the upper layer of the information storage capacitor C in the following process are formed in the memory array and the peripheral circuit. Since the heights are almost the same, the second wirings 52 and 53 disposed on the interlayer insulating film 56, the third wirings 57 and 58 disposed on the interlayer insulating film 63, and Formation of the through holes 60 and 61 connecting between the wirings of the second and third layers is facilitated.
Next, a thin nitride film (not shown) is formed on the surface of the lower electrode 45 by performing heat treatment at 800 ° C. for about 3 minutes in an ammonia atmosphere. Then, as shown in FIG. 34, the upper portion of the lower electrode 45 is formed. On the other hand, a thin Ta ₂ O ₅ (tantalum oxide) film 46 having a thickness of about 14 nm is deposited. The nitride film on the surface of the lower electrode 45 is formed to prevent the polycrystalline silicon film 45A constituting the lower electrode 45 from being oxidized by the next heat treatment. In addition, the Ta ₂ O ₅ film 46 is deposited by, for example, a CVD method using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) as a source gas. Since the Ta ₂ O ₅ film 46 deposited by the CVD method has good step coverage, the Ta ₂ O ₅ film 46 is deposited with almost uniform film thickness over the entire surface of the lower electrode 45 having a three-dimensional cylindrical shape.
Subsequently, the Ta ₂ O ₅ film 46 is heat treated for about 3 minutes in an oxidizing atmosphere at 800 ° C. By performing this high temperature heat treatment, crystal defects in the film are recovered to obtain a high-quality Ta ₂ O ₅ film 46 that is crystallized. As a result, the leakage current of the information storage capacitor C can be reduced, so that a DRAM having improved refresh characteristics can be manufactured.
In addition, the lower electrode 45 of the information storage capacitor C has a three-dimensional cylindrical shape, the surface area thereof is increased, and the capacitor insulating film is composed of a Ta ₂ O ₅ film 46 having a dielectric constant of about 20 to 25. Even if the memory cell is made fine, the amount of accumulated charge sufficient for holding the information can be ensured.
In addition, the lower bit line BL formed before the deposition of the Ta ₂ O ₅ film 46 and the wirings 23 to 26 of the first layer are formed of a W film having good adhesion to the silicon oxide insulating film. Due to the high temperature heat treatment of the Ta ₂ O ₅ film 46, the defect that causes the bit line BL or the wirings 23 to 26 to peel off of the film can be reliably prevented.
Further, since the bit line BL is formed of a W film having high heat resistance, the bit line BL formed with a fine width less than the minimum processing dimension deteriorates or disconnects due to the high temperature heat treatment of the Ta ₂ O ₅ film 46. It is possible to reliably prevent the failure. In addition, a conductive material having high heat resistance (W film / TiN film / Ti film) may be used for the plug 35 inside the contact holes 30 to 35 connecting the MISFET of the peripheral circuit and the wirings 23 to 26 of the first layer. In this configuration, it is possible to prevent the problem of increasing the current and drain resistance of the source and drain due to the high temperature heat treatment of the Ta ₂ O ₅ film 46 and increasing the contact resistance.
The capacitor insulating film of the information storage capacitor C includes, for example, BST, STO, BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT (PbZr _X Ti _1-X O ₃ ), and PLT (PbLa _X Ti _{1- X} O _3), and made of a metal oxide, such as PLZT (steel) may be composed of a dielectric film. These high-strength dielectric films are required to be subjected to high-temperature heat treatment of at least 750 ° C. after forming a film in order to obtain a high-quality film having a small crystal defect as a common property thereof. Therefore, when these high-strength dielectric films are used Even the same effect as above can be obtained.
Next, as shown in FIG. 35, the TiN film was deposited on the Ta ₂ O ₅ film 46 using the CVD method and the sputtering method together, and then the TiN film and the Ta ₂ O ₅ film were subjected to dry etching using a photoresist film as a mask. By patterning 46, an information storage capacitor comprising an upper electrode 47 made of a TiN film, a capacitive insulating film made of a Ta ₂ O ₅ film 46, and a lower electrode 45 made of a polycrystalline silicon film 45A. Element C is completed. Further, by the steps up to this point, the memory cell composed of the memory cell selection MISFET Qs and the information storage capacitor C connected in series thereto is completed. The upper electrode 47 of the information storage capacitor C may be formed of a conductive film other than a TiN film, such as a W film.
Next, as shown in FIG. 36, the interlayer insulating film 56 is formed on the information storage capacitor C, and then the interlayer insulating film 56 and the silicon oxide film of the peripheral circuit are formed using the photoresist film as a mask. 50, the SOG film 39 and the silicon oxide film 39 are etched to form a through hole 54 above the wiring 26 in the first layer. The interlayer insulating film 56 is formed of, for example, a silicon oxide film having a thickness of about 600 nm deposited by CVD.
Next, as shown in FIG. 37, after the plug 55 is formed in the through hole 54, the second wirings 52 and 53 are formed on the interlayer insulating film 56. The plug 55, for example, deposits a Ti film on the upper portion of the interlayer insulating film 56 by sputtering, deposits a TiN film and a W film on the upper portion of the interlayer insulating film 56, and then etches (dry-etches) the films. It forms by leaving only inside 54. The wirings 52 and 53 of the second layer have a Ti film having a thickness of about 50 nm, an Al (aluminum) film having a thickness of about 500 nm, a Ti film having a thickness of about 50 nm, and a film on the upper portion of the interlayer insulating film 56 by sputtering. After a TiN film having a thickness of about 50 nm is sequentially deposited, these films are formed by dry etching using a photoresist film as a mask.
After forming the capacitor insulating film of the information storage capacitor C, since there is no process following high temperature heat treatment, it is used as a material for the second layer wirings 52 and 53 formed on the interlayer insulating film 56. Although heat resistance is inferior to a high melting point metal or its nitride, the electrically-conductive material mainly consisting of Al with low electrical resistance can be used. In addition, since there is no problem of peeling off the film due to the absence of a high temperature heat treatment, the interlayer insulating film 56 is formed when the second wirings 52 and 53 are formed on the interlayer insulating film 56 made of silicon oxide. The Ti film can be used as the barrier metal at the portion where the interface is in contact with
Next, as shown in FIG. 38, after forming the 2nd interlayer insulation film 63 on the wiring 52, 53 of a 2nd layer, the interlayer insulation film (upper) of the information storage capacitor | condenser C The through holes 60 are formed by etching 63 and 56, and the through holes 61 are formed by etching the interlayer insulating film 63 on the upper part of the wiring 53 of the second layer of the peripheral circuit. The second interlayer insulating film 63 is, for example, a silicon oxide film having a thickness of about 300 nm deposited by the CVD method, an SOG film having a thickness of about 400 nm which is spin-coated thereon, and a film deposited thereon by the CVD method. It consists of a silicon oxide film about 300 nm thick. The baking of the SOG film constituting a part of the interlayer insulating film 63 is performed at 400 DEG C in order to prevent deterioration of the capacitive insulating film of the second wiring 52, 53 mainly composed of Al and the information storage capacitor C. It is performed at a temperature of about degree.
Thereafter, the plug 62 is formed inside the through holes 60 and 61, and then the wirings 57, 58 and 59 of the third layer are formed on the interlayer insulating film. This is almost complete. The plug 62 is made of, for example, the same conductive material as that of the plug 55 (W film / TiN film / Ti film), and the wirings 57, 58 and 59 of the third layer are connected to the wiring of the second layer, for example. 52 and 53, the same conductive material (TiN film / Ti film / Al film / Ti film). In addition, a dense insulating film having high water resistance (for example, a two-layer insulating film made of a silicon oxide film and a silicon nitride film deposited by plasma CVD) is deposited on the upper portions of the wirings 57, 58, and 59 of the third layer. However, the illustration is omitted.
As mentioned above, although the invention made by this inventor was demonstrated concretely based on embodiment of this invention, this invention is not limited to the said embodiment, Needless to say that it can be variously changed in the range which does not deviate from the summary. .
The present invention can be applied to a semiconductor integrated circuit device or the like in which a DRAM and a logic LSI or a flash memory are mixed on the same semiconductor chip.
Among the inventions disclosed in the present invention, the effects obtained by the representative ones are briefly described as follows.
According to the present invention, in the DRAM of the capacitor over bit line structure in which the capacitive insulating film of the information storage capacitor is made of a high dielectric material, the wiring of the bit line or the peripheral circuit disposed below the information storage capacitor is used. By forming at least a portion of the base portion in contact with the silicon oxide film with a high melting point metal film other than titanium or cobalt, the adhesion between the wiring of the bit line or the peripheral circuit and the silicon oxide film is improved and is formed when the capacitor insulating film is formed. It is possible to reliably prevent defects that occur at the interface between the bit line, peripheral circuit wiring and the silicon oxide film due to the high temperature heat treatment, thereby improving reliability and manufacturing yield of large-capacity DRAM corresponding to 256 Mbit and later generations. You can.
Further, as a result of a well-known example investigation on "a plug electrode made of Ti / TiN / W" which is one component of the present invention, Japanese Patent Application Laid-Open No. 9-92794 was found.
Although the publication discloses a "plug electrode made of Ti / TiN / W", the bit line and the wiring for the peripheral circuit of the same layer are made of Ti / TiN / W. Therefore, peeling occurs at the interface between the bit line and the underlying oxide film.
From this, it is clear that Japanese Patent Application Laid-Open No. 9-92794 has no problem of peeling, which is completely different from the present invention.

权利要求:
Claims (19)
[1" claim-type="Currently amended] On the top of the silicon oxide-based first insulating film formed on the main surface of the semiconductor substrate, a wiring extending at least partly in contact with the first insulating film is formed, and at least on the second insulating film formed on the wiring A semiconductor integrated circuit device having a capacitor element having a capacitor insulating film partially formed of a high-k dielectric film, wherein the conductive film constituting the wiring includes a high melting point metal, except titanium, at a portion of the conductive film that contacts the first insulating film. A semiconductor integrated circuit device comprising a nitride of a melting point metal.
[2" claim-type="Currently amended] A memory cell selection MISFET having a gate electrode integrally formed with a word line is formed in a first region on a main surface of a semiconductor substrate, and the memory cell is formed on an upper portion of a silicon oxide-based first insulating film covering the memory cell selection MISFET. A bit line electrically connected to one of a source and a drain of the selection MISFET and extending to contact the first insulating film is formed, and the memory cell selection MISFET is formed on the second insulating film formed on the bit line. A semiconductor integrated circuit device having a DRAM in which an information storage capacitor element is formed, which is electrically connected to the other of the source and the drain of the capacitor, and at least part of which has a capacitor insulating film composed of a high dielectric film. The film is formed of a high melting point metal, or a high melting point gold except for titanium, in a portion of the first insulating film that is in contact with the first insulating film. The semiconductor integrated circuit device of the made of a nitride according to claim.
[3" claim-type="Currently amended] The method of claim 2,
And the high dielectric film is a tantalum oxide film subjected to heat treatment for crystallization.
[4" claim-type="Currently amended] The method of claim 2,
And at least a portion of the conductive film constituting the gate electrode of the memory cell selection MISFET is formed of a metal film.
[5" claim-type="Currently amended] The method of claim 2,
A MISFET of a peripheral circuit of the DRAM is formed in a second region on the main surface of the semiconductor substrate, and a gate electrode, source, or drain of the MISFET of the peripheral circuit is formed on top of the silicon oxide-based first insulating layer covering the MISFET of the peripheral circuit. A first layer interconnection is formed which is electrically connected to any one of the wires and extends to contact the first insulating layer, and a conductive film constituting the interconnection of the first layer is formed on the first insulating layer. A semiconductor integrated circuit device characterized in that the portion in contact with the interface is made of a high melting point metal or a nitride of a high melting point metal except titanium.
[6" claim-type="Currently amended] The method of claim 5,
A titanium silicide layer is formed at the bottom of a contact hole that is opened in the first insulating film and electrically connects the wiring of the first layer and the source or drain of the MISFET of the peripheral circuit. Circuitry.
[7" claim-type="Currently amended] The method of claim 5,
And said conductive film constituting each of said bit line and said first layer wiring is a tungsten film.
[8" claim-type="Currently amended] The method of claim 5,
The wiring of the first layer is formed inside the contact hole, and is a source or a drain of the MISFET of the peripheral circuit through a plug composed of a laminated film of a titanium film and a barrier metal film or a laminated film of a titanium film and a barrier metal film and a tungsten film. And electrically connected to the semiconductor integrated circuit device.
[9" claim-type="Currently amended] The method of claim 5,
And the gate electrode of the MISFET of the peripheral circuit is made of a metal film.
[10" claim-type="Currently amended] The method of claim 5,
And the first insulating film is a spin-on-glass film or a silicon oxide film deposited by a CVD method.
[11" claim-type="Currently amended] The method of claim 5,
The second layer wiring electrically connected to the first layer wiring is formed on the silicon oxide-based third insulating film formed on the information storage capacitor, and the conductive lines constitute the second layer wiring. And the film is a titanium film at least in contact with the third insulating film.
[12" claim-type="Currently amended] (a) After forming a silicon oxide-based first insulating film on the main surface of the semiconductor substrate, a portion of the first insulating film in contact with the first insulating film on the first insulating film is a high melting point metal or titanium except for titanium Depositing a conductive film made of a nitride of a high melting point metal, including
(b) forming a second insulating film over the wiring by forming a wiring extending at least a part thereof in contact with the first insulating film by patterning the conductive film;
(c) forming a capacitor formed of a first electrode, a dielectric film, and a second electrode on the second insulating film,
And the forming step of the capacitor device comprises a heat treatment step for improving the film quality of the dielectric.
[13" claim-type="Currently amended] (a) forming a memory cell selection MISFET constituting a memory cell of a DRAM in a first region on a main surface of a semiconductor substrate, and forming a MISFET constituting a peripheral circuit of the DRAM in a second region on a main surface of the semiconductor substrate; fair,
(b) forming a silicon oxide-based first insulating film on each of the memory cell selection MISFET and the peripheral circuit MISFET;
(c) a first contact hole is formed in the first insulating film on at least one of the source and the drain of the memory cell selection MISFET, and the first insulating film on each of the source and the drain of the MISFET of the peripheral circuit. Forming a second contact hole in the first circuit and forming a third contact hole in the first insulating film above the gate electrode of the MISFET of the peripheral circuit;
(d) the peripheral circuit exposed to the bottom of the second contact hole by depositing a titanium film in each of the second contact hole and the third contact hole and on top of the first insulating film, and then heat treating the semiconductor substrate. Forming a titanium silicide layer on each surface of the source and the drain of the MISFET,
(e) after depositing a barrier metal film or a laminated film of a high melting point metal film excluding the barrier metal film and titanium on top of the titanium film including the inside of each of the second contact hole and the third contact hole, (1) forming a plug in each of the second contact hole and the third contact hole by removing the barrier metal film or the laminated film over the insulating film together with the titanium film;
(f) depositing a conductive film made of a high melting point metal other than titanium or a nitride of a high melting point metal, at least a portion of the first insulating film being in contact with the first insulating film;
(g) forming a bit line electrically connected to one of a source and a drain of the memory cell selection MISFET through the first contact hole by patterning the conductive film, and forming the second contact hole or the third contact. Forming a wiring of the first layer of the peripheral circuit electrically connected to the MISFET of the peripheral circuit through the hole;
(h) forming a data storage capacitor device comprising a first electrode, a dielectric film, and a second electrode on the second insulating film;
And the forming step of the capacitor device comprises a heat treatment step for improving the film quality of the dielectric film.
[14" claim-type="Currently amended] The method of claim 13,
A conductive film constituting each of the gate electrode of the memory cell selection MISFET and the gate electrode of the MISFET of the peripheral circuit is a semiconductor film comprising a low resistance polycrystalline silicon film, a barrier metal film, and a tungsten film doped with impurities. Method of manufacturing integrated circuit device.
[15" claim-type="Currently amended] The method of claim 13,
And the wiring of the first layer of the bit line and the peripheral circuit is a tungsten film.
[16" claim-type="Currently amended] The method of claim 13,
And said dielectric film is made of a metal oxide.
[17" claim-type="Currently amended] The method of claim 16,
The metal oxide is tantalum oxide manufacturing method of a semiconductor integrated circuit device.
[18" claim-type="Currently amended] The method of claim 13,
And a heat treatment temperature for improving the film quality of the dielectric film is 750 占 폚 or higher.
[19" claim-type="Currently amended] (a) forming a memory cell selection MISFET constituting a DRAM memory cell in a first region on a main surface of a semiconductor substrate, and forming a MISFET constituting a peripheral circuit of the DRAM in a second region on a main surface of the semiconductor substrate; fair,
(b) forming a silicon oxide-based first insulating film on each of the memory cell selection MISFET and the peripheral circuit MISFET;
(c) a first contact hole is formed in the first insulating film on at least one of the source and the drain of the memory cell selection MISFET, and the first insulating film on each of the source and the drain of the MISFET of the peripheral circuit. Forming a second contact hole in the first circuit and forming a third contact hole in the first insulating film above the gate electrode of the MISFET of the peripheral circuit;
(d) the peripheral circuit exposed to the bottom of the second contact hole by heat-treating the semiconductor substrate after depositing a cobalt film in each of the second contact hole and the third contact hole and on top of the first insulating film. Forming a cobalt silicide layer on each surface of the source and the drain of the MISFET,
(e) after depositing a barrier metal film or a laminated film of a high melting point metal film excluding the barrier metal film and cobalt on an upper portion of the cobalt film including each of the second contact hole and the third contact hole, (1) forming a plug in each of the second contact hole and the third contact hole by removing the barrier metal film or the laminated film over the insulating film together with the cobalt film;
(f) depositing a conductive film formed of a nitride of a high melting point metal or a high melting point metal other than cobalt, at least a portion of the first insulating film in contact with the first insulating film;
(g) By patterning the conductive film, a bit line is electrically connected to one of a source and a drain of the memory cell selection MISFET through the first contact hole, and the second contact hole or the third contact hole is formed. Forming a wiring of the first layer of the peripheral circuit electrically connected to the MISFET of the peripheral circuit through
(h) forming an information storage capacitor device including a first electrode, a dielectric film, and a second electrode on the second insulating film,
And the forming step of the capacitor device comprises a heat treatment step for improving the film quality of the dielectric film.

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同族专利:

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公开号 | 公开日

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US20010023099A1|2001-09-20|

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US20020182798A1|2002-12-05|

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JPH11214644A|1999-08-06|

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US6399438B2|2002-06-04|

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TW508798B|2002-11-01|

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JP3686248B2|2005-08-24|

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KR100699335B1|2007-03-26|

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US6638811B2|2003-10-28|

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US6215144B1|2001-04-10|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1998-01-26|Priority to JP98-012614

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1998-01-26|Priority to JP01261498A

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1999-01-22|Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼

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1999-08-25|Publication of KR19990068074A

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2007-03-26|Application granted

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2007-03-26|Publication of KR100699335B1

优先权:

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申请号 | 申请日 | 专利标题

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JP98-012614|1998-01-26|

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JP01261498A|JP3686248B2|1998-01-26|1998-01-26|Semiconductor integrated circuit device and manufacturing method thereof|